University of Salzburg
Department of Computer Sciences
Jakob-Haringer-Str. 2, 5020 Salzburg, Austria
Phone: +43 662 8044 6405
- real-time and embedded systems
- modeling and simulation
- logical execution time (LET)
- functional programming
- software engineering
Functional Programming (VO/PS)
Bachelor Project (PR)
Databases I (PS)
Distributed Systems (PS)
Software Techniques (PS)
Harnessing Concurrency in Synchronous Block Diagrams to Parallelize Simulation on Multi-core Hosts, WSC, National Harbor, Maryland, USA, 2019.
A TrueTime Extension for Instruction-level Timing and Multi-stack Support, IECON, Lisbon, Portugal, 2019.
Platform-Awareness in Model-Based Development, MathWorks Research Summit, Newton/MA, USA, 2019.
Subjecting Legacy Simulink Models to Timing Speciﬁcations, CyPhy@EMSOFT, Turin, Italy, 2018.
Logical Execution Time (LET) for Legacy and Model-based Applications, Dagstuhl Seminar 18092, Schloss Dagstuhl, Germany, 2018.
Simulating Execution Time Variations in MATLAB/Simulink, Winter Simulation Conference (WSC), Las Vegas, USA, 2017.
Simulating Preemptive Scheduling with Timing-aware Blocks in Simulink, DATE, Lausanne, Switzerland, 2017.
A. Naderlinger. Harnessing Concurrency in Synchronous Block Diagrams to Parallelize Simulation on Multi-core Hosts. In Proceedings of the 2019 Winter Simulation Conference, WSC ’19, pages 702-713, National Harbor, Maryland, USA, December 08 - 11, 2019.
A. Naderlinger, M. Moser. A TrueTime Extension for Instruction-level Timing and Multi-stack Support. In IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society, Lisbon, Portugal, October 14-17, 2019.
A. Naderlinger. Subjecting legacy Simulink models to timing speciﬁcations. In R. Chamberlain, W. Taha, and M. Törngren, editors, Cyber Physical Systems. Model-Based Design (CyPhy@EMSOFT 2018), volume 11615 of Lecture Notes in Computer Science (LNCS). Springer Berlin Heidelberg, 2019.
A. Naderlinger, S. Resmerita, and W. Pree. LET for Legacy and Model-based Applications. In R. Ernst, S. Kuntz, S. Quinton, and M. Simons, editors, The Logical Execution Time Paradigm: New Perspectives for Multicore Systems , volume 8, pages 135–138. Schloss Dagstuhl–Leibniz-Zentrum fuer Informatik, Dagstuhl, Germany, 2018
A. Naderlinger. Simulating execution-time variations in MATLAB/Simulink. In Proceedings of the 2017 Winter Simulation Conference, WSC ’17, Las Vegas, USA, December 03 - 06, 2017.
S. Resmerita, A. Naderlinger, and S. Lukesch. Efficient realization of logical execution times in legacy embedded software. In Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, MEMOCODE 2017, Vienna, Austria, September 29 - October 02, 2017, pages 36–45, 2017.
A. Naderlinger. Simulating preemptive scheduling with timing-aware blocks in Simulink. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pages 758–763, 2017.
J. Hennig, H. von Hasseln, H. Mohammad, S. Resmerita, S. Lukesch, and A. Naderlinger. Towards Parallelizing Legacy Embedded Control Software Using the LET Programming Paradigm. In 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), volume WIP, Vienna, Austria, 2016.